1. Field of the Invention
The present application relates to, e.g., computation systems and methods and, in some preferred embodiments, to novel memory based computations systems and methods for high performance and/or fast operations logic circuits.
2. Background Discussion
A variety of high performance logic circuits are known. Exemplary circuits include, e.g., Adders, Multipliers, Fast Fourier Transform (FFT) Compilers, Finite Impulse Response (FIR filters), etc.
By way of example, in common digital signal processor (DSP) devices, a multiplication unit is used to implement algorithms, such as, by way of example, filtering, etc. Often, a digital multiplier has a substantial impact on the performance. With the increasing demands for, among other things, high-performance portable systems with, e.g., multimedia capabilities, low power design requirements are also of increased importance. Digital multipliers are used in variety of system applications, such as, e.g., digital filters, correlators and neural networks, as well as in a variety of other applications. As just one other illustrative example, digital finite impulse response (FIR) filters often form a basis for many digital signal processing system applications.
As described below, in certain applications unrelated to high performance applications, ROM (Read only Memory) based design has been employed. In this regard, ROM based design has been employed in Field Programmable Gate Array (FPGA) architecture, where basic gates like NAND, NOR, etc., have been implemented following this ROM based design approach. In addition, a similar approach has also been used to generate series functions like logarithmic numbers and sinusoidal functions. However, such known applications are slow and consume a considerable amount of energy. One major reason for slower operation and higher energy consumption in such ROM based design in FPGA architecture is the use this approach for achieving reconfigurability. For this purpose, mainly basic gates are implemented using very small ROM structures (typically, 4 to 16 bit), which requires an increased number of transistors as compared to a conventional CMOS gate.
By way of example, FIG. 2 depicts an existing look-up-table-based configuration logic cell. In particular, the circuit shown in FIG. 2 has a two input gate, whose functions can be defined by appropriately writing the memory cells SW0 to SW3. Accordingly, by changing the memory content, the function can be accordingly changed. In the figure, input A and input B are two inputs that are used to access one of the four memory cells SW0 to SW3 for the right output.
However, implementing small functions like NAND or NOR using this technique, as in the case of FPGA, results in a slower operation and a higher power operation than with a conventional logic gate alone, as well as a larger area. This is because a two input NAND gate (see, e.g., FIG. 3), by way of example, requires only four transistors in CMOS design, which is fast and consumes less power.
Similarly, in the context of implementing series functions using this approach, this typically involves the employment of a large ROM size, which results in large delays (e.g., accessing the memory), increased area usage, and increased power usage.
As set forth above, the existing ROM designs do not relate to high-activity, high performance applications. There remains a continued need for improvements in high performance logic circuits, including, for example, Adders, Multipliers, Fast Fourier Transform (FFT) Compilers, Finite Impulse Response (FIR filters), etc. —to name a few.